Fabricating a semiconductor carrier for an integrated circuit module is currently achieved by one of two fundamentally different options. One technique involves creating the semiconductor (e.g.—Si)-through via first (=via first (VF)) and the other creates the semiconductor-through via last (=via last (VL)). The VF approach is built using a full thickness wafer until nearly the end of the process. The VL process builds the BEOL first, thins the wafer to thickness of about 50-150 μm followed by the through wafer via definition. The VL application requires that the wafer be laminated onto a glass handler wafer after the BEOL build completion and before wafer thinning and through via RIE. The thinned wafer with the laminated glass handler wafer is diced after the through via fill, BLM, and C4 depositions. It is for these singulated thin Si-carriers that the process of glass carrier wafer removal is designed. This removal process takes place after the Si-carrier with the laminated glass is C4 joined to a substrate.
Difficulties are encountered in the removal process for VL and VF fabrication because the thinned wafer renders the carrier vulnerable to cracking, especially at the edges. This vulnerability is exacerbated by the stress placed on the carrier by the C4 balls used in the joining to the substrate.
A method to fabricate thinned Si-chips with C4 balls is to use the 3M Wafer Support System for ultra thin wafer backgrinding. In this approach a wafer is adhered onto a glass handler wafer, which is larger than the Si-wafer, using UV curable liquid adhesive with thermal stability of about 200° C. The Si-wafer (without through vias) is thinned and mounted onto the dicing tape on a frame. The adhesive—glass wafer interface is ablated using laser radiation followed by whole glass wafer removal off the adhesive backed thinned Si-wafer. The residual UV resin film is peeled off the thinned, bumped Si-wafer which is left on the framed dicing tape for chip singulation. After singulation the chips are joined to a substrate as is well known in the art. Chip pick and place operation will set limits to the thickness of the thinned Si-chip, which is likely to about 150 μm-200 μm to avoid chip fracture during handling and chip joining.
This type of method is used without the C4-balls to join thinned full wafers to each other in the 3D-packaging approach.
In these approaches the glass wafer is larger than the Si-wafer itself. This makes it impossible to do further CMOS BEOL processing on the Si-wafer post lamination to the glass handler wafer, as most of the standard CMOS tooling cannot handle the larger size.
It should also be noted that in the advanced applications, such as the Si-carrier application, the carrier dimensions can be several centimeters per side (i.e. significantly larger than a standard Si-chip). The size combined with the Si-thickness down to the BEOL thickness will make it impossible to pick these carriers off the dicing tape and flip-chip join them without damage to the carrier. Thus the existing methods are not applicable for the processing or flip-chip joining of the large, thin Si-carriers.